This invention relates to semiconductor devices and their manufacture and, more particularly, to the testing of such devices including the area of gate dielectric integrity testing.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, manufacturing processes becomes more difficult. As the manufacturing processes become more difficult, the importance of accurate testing procedures increases significantly.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such semiconductor devices generally include a semiconductor substrate on which active devices and passive devices are formed. Such active silicon-based devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors. While the particular structures of a given active device can vary between device types, a MOS transistor generally includes source and drain regions and a gate electrode that modulates current in a channel between the source and drain regions. The gate electrode is typically insulated from the source and drain regions and the channel using a dielectric, such as an oxide.
A common passive semiconductor device is a capacitive device, or capacitor. The structure of a typical capacitive device includes, for example, two gate electrodes separated by a dielectric, such as an oxide. In integrated circuits, capacitive devices are commonly implemented using a MOS transistor with its source and drain terminals interconnected. For the device to function properly, the dielectric acts to prevent a voltage differential between the two terminals from discharging directly from terminal to another.
In the manufacture of such integrated circuits, several different types of tests are required to ensure the quality of the product. One important test is to ensure the integrity of the gate oxide. A typical gate oxide integrity test is performed on a process monitor, which is a test structure placed next to circuit die locations on the silicon wafer. The oxide quality is assessed by stressing the oxide using the maximum allowable voltage across the oxide and comparing the measured leakage current to an acceptance limit that is based on the area of the gate oxide test device and other factors which define acceptable versus unacceptable leakage levels.
Modern integrated circuits are dominated by digital logic area, although more analog functions are being incorporated into the circuits. This trend will continue as the xe2x80x9csystem-on-a-chipxe2x80x9d concept draws more and more functionality into a single integrated circuit design. In establishing acceptable leakage levels, analog and digital requirements diverge. The dominant digital logic can withstand a certain amount of leakage in the transistors and remain fully functional. This leakage is undesirable since standby currents increase dramatically. However, the circuits can still function normally at leakage levels which are unacceptable for analog circuitry. Since the digital logic dominates current integrated circuit designs, the leakage test structures are sized to adequately measure leakage for the digital logic.
Analog functional blocks, such as a phase-locked loop (PLL), suffer from bias shifts and leakage from high-impedance nodes and, at these leakage levels, the digital logic areas are not impacted. In analog blocks, this leakage can, and usually does, result in significant performance degradation. Therefore, the normal gate oxide leakage screening levels may not be sufficiently stringent to flag problems in analog blocks. PLLs and other functional blocks that contain large integrated capacitors are especially susceptible to gate oxide leakage. To achieve an acceptable capacitance value within a reasonable amount of silicon area, these large integrated capacitors are commonly built using gate oxide. For this reason, gate oxide leakage can be an important factor for large integrated capacitors. A particular type of fully-integrated PLL contains a large loop filter capacitor for which leakage current well below 0.1 nanoamp per 100 picofarads may be required.
As more devices are required to be fit into smaller areas of silicon, the device sizes will continue to shrink with each new generation of technology. With each new generation, the logic gate oxide area shrinks per individual device, but the analog transistor gate oxide area is often driven by other factors, such as tight matching and a stringent noise budget. The factors require that the analog transistor not scale in size with the digital transistors. The required capacitance area is set by the design value of the capacitance in picofarads. This capacitance area also does not scale with the digital logic. For these reasons, test structures may diverge from the needs of analog functional blocks.
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements concerning dielectric integrity testing of semiconductor structures. One specific implementation is directed to a process of testing the dielectric integrity of a capacitive structure coupled to a current-sensitive node in a semiconductor device. The process involves stressing the capacitive device by presenting a voltage differential across its terminals; isolating the current-sensitive node from other current paths; measuring the leakage current at the current-sensitive node; comparing the measured leakage current at the current-sensitive node with a reference level; and determining therefrom a quality factor indicative of the dielectric integrity in the capacitive device.
A more specific implementation of the present invention is directed to a method for testing dielectric integrity in a PLL capacitor circuit that forms part of controlled oscillator PLL circuit having a test mode. The PLL capacitor circuit has a capacitive device coupled between two terminals and coupled to a current-sensitive node in the controlled oscillator PLL circuit. The method involves: causing the controlled oscillator PLL circuit to enter the test mode; while in the test mode, stressing the capacitive device by presenting a voltage differential comparable to a supply voltage across the two terminals; isolating the current-sensitive node from other current paths; measuring the leakage current at the current-sensitive node; comparing the measured leakage current at the current-sensitive node with a reference level and determining therefrom a quality factor indicative of the dielectric integrity in the capacitive device.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.